Charles Lee Powell Chair in Electrical and Computer Engineering and Computer Science
Professor of Electrical and Computer Engineering

Category: Past Projects

  • USC SPORT: System Power Optimization and Regulation Technologies

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    Project URL: SPORT Lab We investigate power estimation and low power design of CMOS VLSI circuits and systems all different abstraction levels. Our emphasis is on developing mathematically rigorous analysis and optimization algorithms and power-aware design methodologies for solving various problems of practical interest and import. Our most recent work has focused on energy-efficient enterprise computing,…

  • Accurate gate modeling under variation with neural networks

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    Deeply scaled FinFET devices are the optimal choice for low power applications based on their specific characteristics over conventional MOSFET devices. However, these devices are very sensitive to process variation and exhibit non-linear timing and power behavior. Due impact of several number of variation parameters, it is not-practical for the conventional industrial characterization process (e.g.…

  • Energy-aware Task Scheduling in Real-Time Systems with Hard Deadline Constraints

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    Energy efficiency is one of the most critical design criteria for modern embedded systems such as multiprocessor system-on-chips (MPSoCs). Dynamic voltage and frequency scaling (DVFS) and dynamic power management (DPM) are two major techniques for reducing energy consumption in such embedded systems. Furthermore, MPSoCs are becoming more popular for many real-time applications. One of the…

  • Margin and yield calculation for Single Flux Quantum (SFQ) logic cells

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    Sponsor: Intelligence Advanced Research Projects Activity (IARPA). In this project novel margin calculation methods are introduced for SFQ cels. These methods calculate a set of parameter margins for each logic cell such that if all parameters lie within the boundary of the calculated margins, parametric yield values are near one.

  • Collaborative Intelligence

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    Sponsor: Latency and energy consumption of DNN queries can be significantly improved by splitting the workload between the mobile and cloud. Real-time scheduling of computations between the mobile and cloud and efficient feature communication are studied in this project.Related work:

  • Meta-learning

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    Sponsor: Meta-learning focuses on learning over the task space rather than instance space by training a general model which is able to quickly adapt to new unseen tasks. The implications of fast adaptation to new unseen tasks can also be effective on the traditional paradigm of neural networks training. Modeling generalization, few-shot learning, and task…

  • Improving the Energy Efficiency and Lifetime of Coarse-Grained Reconfigurable Architectures

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    Sponsor: The error resiliency of applications such as media processing has provided designers with a new technique called approximate computing (AC), which abandons exactness of computation in favor of improved efficiency. In functional approximation, which is our focus here, a more simpler function different than the actual design is implemented that can be generated manually…

  • Towards Green Communication: Energy Efficient Solutions for the Next Generation Network

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    Sponsor: This project investigates energy efficiency problems in next generation network. Intelligent power m anagement solutions are studied to maximize the utility objective. For example, dynamic switching of base stations, smart scheduling for renewable energy, content caching and cooperative transmission.Related work:

  • VINE: A Variational Inference-Based Bayesian Neural Network Engine

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    Sponsor: Defense Advanced Research Projects Agency. The primary goal is to develop a Bayesian Neural Network (BNN) with an integrated Variational Inference (VI) engine to perform inference and learning under uncertain or incomplete input and output features. A secondary goal is to enable robust decision making under noise and variability in the observed data and without…

  • Performance and Power Efficiencies of Network On-Chip

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    Sponsors: National Science Foundation (the Software and Hardware Foundations). Improving the Quality of Service in Application Mapping on NoC-Based Multi-Core Platforms With tens to possibly hundreds of cores integrated in current and future multiprocessor systems-on-chips (MPSoCs) and chip-multiprocessors (CMPs), multiple applications usually run concurrently on the system. However, existing mapping methods for reducing overall packet latency…