Author: admin
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Design of Modular Multiplication
Development of efficient Montgomery/Barrett modular multiplication to reduce computation latency or save hardware area. It includes a new algorithm to parallelize the computation of quotient and intermediate result, speed up the expression (A+B)*C, etc. Related work:
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Algorithm-Architecture Co-Design for Energy-Efficient and Reliable Machine Learning Models
Sponsor: National Science Foundation (NSF) The broader scope of this research includes: a) Energy-efficient architecture and algorithm co-design for DNN training to yield compressed models, b) Efficient model compression to retain its robustness, c) Model compression of brain-inspired deep SNNs.Related work:
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Energy-Efficient, Low-Latency Realization of Neural Networks Through Boolean Logic Minimization
Sponsor: TBD To cope with computational and storage complexity of deep neural networks, this project focuses on a training method that enables a radically different approach for realization of deep neural networks through Boolean logic minimization. The aforementioned realization completely removes the energy-hungry step of accessing memory for obtaining model parameters, consumes about two orders…
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Placement and Clock Network Synthesis for Single Flux Quantum (SFQ) Logic Circuits
Sponsor: Intelligence Advanced Research Projects Activity (IARPA) In this project new algorithms for placement and clock network synthesis for large scale SFQ circuits a re developed and implemented. The goal is to maximize the circuit performance in terms of maximum clock frequency, considering special characteristics of SFQ technology.
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Minimizing the longest routing wires of large-scale flux circuits
Sponsor: Intelligence Advanced Research Projects Activity (IARPA) Development of a routing tools for single flux quantum (SFQ) circuits. The routing tools aims at finding connection wire paths of all nets of a SFQ circuit while satisfying design rule check. The following is for elaboration: The routing tools are further optimized to identify critical nets with…
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Efficient Synthesis and Realization of Single Flux Quantum (SFQ) Logic Circuits
Sponsor: Intelligence Advanced Research Projects Activity (IARPA) This project is about designing suitable computer aided-design (CAD) software tools to support design automation of superconducting single flux quantum circuits. The main focus is on logic and behavioral level synthesis. This includes designing algorithms and implementing them using C/C++ and Python programming languages, and it involves verification…
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Optimization of Single Flux Quantum (SFQ) Logic Cells
Sponsor: Intelligence Advanced Research Projects Activity (IARPA) Due to fabrication uncertainties, it is important to have cells that can tolerate variations. For this project, we introduce a hybrid optimization algorithm for improving critical parameter margins of the cells. With Monte Carlo simulations, we show that increased critical margins improve the parametric yield. Related work:
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Advanced Cell Design, Characterization and Re-configurable Circuits for Single Flux Quantum Technology
Sponsor: Intelligence Advanced Research Projects Activity (IARPA) Due to the lack of three-terminal device like MOSFET in CMOS circuits in superconducting electronics, it is difficult to conceive a superconducting FPGA which provides significantly cheaper solutions for various applications. Our work is focused on proposing designing FPGA for superconducting circuits using magnetic Josephson junctions and energy-efficient…
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Intelligent Arithmetic Circuit Recognition
Sponsor: Intelligence Advanced Research Projects Activity (IARPA) we address the problem of deriving a functional description of a circuit from an unstructured netlist by leveraging deep learning and circuit representations based on convolutional neural networks (CNNs). In doing so, we are motivated by the state-of-the-art performance of machine learning (ML) techniques, based on both convolutional…
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Verification Techniques for Single Flux Quantum (SFQ) Circuits
Sponsor: Intelligence Advanced Research Projects Activity (IARPA) Objective of this project is to develop the post-synthesis verification techniques for SFQ circuits. As part of this work, we developed a logical equivalence checking (LEC) approach that would check the equivalence of a post-synthesis gate level netlist of a target SFQ circuit against an initial Boolean network…