Verification Techniques for Single Flux Quantum (SFQ) Circuits

Sponsor: Intelligence Advanced Research Projects Activity (IARPA)

Objective of this project is to develop the post-synthesis verification techniques for SFQ circuits. As part of this work, we developed a logical equivalence checking (LEC) approach that would check the equivalence of a post-synthesis gate level netlist of a target SFQ circuit against an initial Boolean network representation of the same circuit. In addition to LEC, we work on a semi-formal verification framework for SFQ circuits in the UVM standard. The SFQ logic-focused framework was developed with the best-practice verification methodology of the Universal Verification Methodology (UVM) standard in mind and is easily portable for verifying other SFQ circuit designs.Related work: