Author: admin

Battery Aware Hierarchical Wireless Sensor Network for Distributed Data Collection Lifetime-Aware Hierarchical Wireless Sensor Network Architecture with Mobile Overlays — With power efficiency and lifetime awareness becoming critical design concerns, we focus on energy-aware design of different layers of the WSN protocol stack. In a RAW-07 conference paper, we presented and analyzed a hierarchical wireless sensor…

Hardware/Software Support and Algorithms for Dynamic Backlight Scaling in TFT LCDs B2Sim: A Fast Micro-Architecture Simulator Based on Basic Block Characterization — State-of-the-art architectural simulators support cycle accurate pipeline execution of application programs. However, it takes days and weeks to complete the simulation of even a moderate-size program. During the execution of a program, program behavior…

Stochastic Approaches for Dynamic Thermal Management in High Performance Microprocessor Chips A Stochastic Local Hot Spot Alerting Technique — In an ASPDAC-08 conference paper, we addressed the questions of how and when to identify and issue a hot spot alert in a microprocessor. These are important questions since temperature reports by thermal sensors may be erroneous,…

Minimizing Leakage Power in CMOS Designs Minimizing Leakage Power in CMOS: Technology and Design Issues — This tutorial given at EPFL in July 2008 focuses on circuit techniques and design methods to accomplish this goal. The first part of the presentation provides an overview of basic physics and technology and scaling trends that have resulted in…

Performance and Reliability Analysis and Optimization in Sub-45nm CMOS Circuits Probabilistic Error Propagation in a Logic Circuit Using the Boolean Difference Calculus — A gate level probabilistic error propagation model is presented which takes as input Boolean function of the gate, signal probability, the probability for signal being “1”, and error probability at the gate inputs,…

Design Methodologies and Techniques for Optimizing Power Consumption and Performance in Pipeline Circuits A Mathematical Solution to Power Optimal Pipeline Design by Utilizing Soft Edge Flip Flops — In an ISLPED-08 paper, we presented a technique to address the problem of reducing the power consumption in a synchronous linear pipeline, based on the idea of utilizing…

Optimal Design of Power Delivery Network for System on Chip Design of an Efficient Power Delivery Network in an SoC to Enable Dynamic Power Management In an ISLPED-07 paper, we introduced a new technique to design the power delivery network for a SoC design to support dynamic voltage scaling. In this technique the power delivery network…

Power Efficient SRAM Cell and Array Design Low-Leakage SRAM Design in Deep Submicron Technologies — This January-2008 presentation has two parts. In the first part, a method based on dual-Vt and dual-Tox assignment is presented to reduce the total leakage power dissipation of SRAMs while maintaining their performance. The proposed method is based on the observation…

Design Techniques and Tools to Enable and Enhance Coarse-Grain Power Gating in ASIC Designs Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting — Current state-of-the-art sleep transistor sizing algorithms minimize the total sleep transistor width subject to a maximum IR voltage drop on the virtual node of each MTCMOS switch cell. In these approaches, the DC…

Statistical Static Timing Analysis and Circuit Optimization: A Current Source Model-Based Approach Recent Results of the Current Source Model-Based Approach for Timing Analysis — Our work focuses on the development of an accurate current source model of a CMOS logic cell with extensions to handle multiple input switching and statistical parameter variability. The work also includes…