Statistical Static Timing Analysis

Statistical Static Timing Analysis and Circuit Optimization: A Current Source Model-Based Approach

Recent Results of the Current Source Model-Based Approach for Timing Analysis — Our work focuses on the development of an accurate current source model of a CMOS logic cell with extensions to handle multiple input switching and statistical parameter variability. The work also includes development of efficient methods to generate the CSMs of logic cells, which are typically present in a standard cell library. The work addresses integration of CSMs of logic cells with a waveform propagation engine in order to produce a highly efficient and robust CSM-based static timing analyzer.