Apollo: Adaptive Power Optimization and Control for the Land Warrior

Project URL: Apollo Testbed

The Apollo project aims at significantly reducing power dissipation of next-generation mobile DoD computing and communication systems by means of operating system-directed power management, power-aware software compilation, and system-level synthesis and optimization of the integrated hardware/software platform subject to performance and quality-of-service constraints.

We consider dynamic power management techniques and study the problem of determining optimal management policies for a variety of system models. In particular, we focus on operating system (OS) directed control policies and seek to develop realistic models of the hardware and software components and the system environment in the Land Warrior System (LWS). We characterize power consumption of common arithmetic logic and memory blocks and develop instruction-level power macro-models for the StrongARM microprocessor and TI’s digital signal processor 320c-5410 in addition to the major subsystems in the (next-generation) LWS.

We investigate the problem of developing techniques for power-conscious architectural organization and optimization techniques targeting a StrongARM-based hardware platform that we are constructing based on the Intel’s Assabet and Neponset boards plus a number of external devices. This platform is called the Apollo Testbed (AT). We also develop system and application software for the AT. This task will include development of the ARMLinux drivers for all external devices, the “map” application, and the utility software needed for the AT usage scenario that is provided to us by the IPM team of the Army CECOM.

We develop encoding techniques to minimize the switching activity on a time-multiplexed Dynamic RAM (DRAM) address bus. We develop redundant (i.e., with INVERT bit) memory bus encoding techniques that reduce the switching activity on the bus between the FLASH memory and the processor. The proposed codes are expected to reduce power dissipation on the memory bus by a factor of two or more. We develop algorithms and techniques for power optimization of the FLASH and main memory hierarchy in the AT. More precisely, we explore use of different data representations for the images stored in the map database so as to reduce power-consuming accesses to the FLASH memory (which acts as the secondary storage in the AT) at the expense of more intensive computations on the SA 1110. We study and analyze the impact of various architectural optimization techniques on the power saving of the AT. Such techniques include power optimization and control for the LCD, the camcorder, and the network (wireless LAN) interface card.

This work is done in collaboration with Prof. Niraj Jha of Princeton University. Dr. Jha will tackle both periodic and aperiodic task graphs, automatically generate and transform task graphs from the system specification, estimate system power and synthesize low-power system architectures. The system synthesis tools that will be developed include all supporting databases and simulation engines. The tools will synthesize a given system specification written in C or Hardware Description Language (HDL) into a low-power system architecture. He will analyze, model and optimize the power consumed by a real-time operating system (RTOS). He will develop behavioral synthesis tools for low power application-specific integrated circuits (ASICs). The work will be implemented on top of the Princeton university’s synthesis system called IMPACT. Additional research topics are common-case computation, leakage power optimization and run-time adaptation in behavioral synthesis for low power.