Optimal Design of Power Delivery Network for System on Chip

Spornsor:Defense Advanced Research Projects Agency, National Science Foundation, and the Semiconductor Research Corporation.

Project Summary: While power modeling and dynamic power management in various VLSI platforms have been heavily investigated, there is one critical factor that has often been overlooked, and that is the power conversion efficiency of the power delivery network (PDN) in the platforms. The PDN provides power from a power source (e.g., battery) to all modules in a platform. In reality, voltage regulators (VRs), which play a pivotal role in the PDN, inevitably dissipate power, and power dissipations from all VRs can result in a considerable amount of power loss. This is mainly because of the characteristics of the VRs that their efficiency can drop dramatically under adverse load conditions (i.e., out-of-range output current levels). This project aims to improve the power conversion efficiency of the PDN. We have been proposing optimization methods that minimize the power loss of the PDN, thereby maximizing the system-wide power savings.

Optimizing the PDN in Smartphone Platforms

In a series of papers published in proceedings of the ISLPED-12 and IEEE T. CAD-14, we introduced optimization methods to improve the power conversion efficiency of the PDNs in mobile (smartphone) platforms. Starting from detailed models of the VR designs, two optimization methods have been presented: (i)static switch sizing to maximize the efficiency of a VR under statistical loading profiles, and (ii) dynamic switch modulation to achieve high efficiency enhancement under dynamically varying load conditions. To verify the efficacy of the optimization methods in actual smartphone platforms, we also presented a characterization procedure for the PDN. The procedure is as follows:(i) group the modules in the smartphone platform together and use profiling to estimate their average and peak power consumption levels, and (ii) build an equivalent VR model for the power delivery path from the battery source to each group of modules and use linear regression to estimate the conversion efficiency of the corresponding equivalent converter. Experimental results demonstrated the efficacy of the proposed methods.Related work:

Dynamic Reconfiguration of VRs in Multicore Platforms

In DATE-14 paper, we focused on the dynamic control of the multiple VRs in chip multicore processor (CMP) platforms that support per-core DVFS. Starting with a proposed platform with a reconfigurable VR-to-core power distribution network (PDN), two optimization methods have been presented to maximize the system-wide energy savings: (i) reactive VR consolidation to reconfigure the PDN for maximizing the power conversion efficiency of the VRs under the pre-determined DVFS levels for the cores, and (ii) proactive VR consolidation to determine new DVFS levels for maximizing the total energy savings without any performance degradation. Results from detailed simulations based on realistic experimental setups demonstrated significant VR energy loss reduction and total energy saving.Related work: