Charles Lee Powell Chair in Electrical and Computer Engineering and Computer Science
Professor of Electrical and Computer Engineering

Near-Threshold Computing and Deeply-Scaled Devices

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Sponsors: DARPA PERFECT program, and National Science Foundation (the Software and Hardware Foundations).

Device Simulation and Performance Prediction for Deeply-Scaled FinFET Devices

As the geometric dimension of transistors scales down, FinFET devices are proved to better address the challenges facing conventional planar CMOS devices. Due to manufacturing limitations, deeply-scaled FinFET devices below 10nm feature size have not been manufactured. Nevertheless, it is crucial to investigate the performance of such devices with lower feature sizes in order to shed some light on further studies on novel process techniques and circuit structures. In our work, the 7nm-gate-length FinFET structure models are built up and simulated using the Synopsys TCAD tool suite. We generate the predicted performance of the FinFET devices with different design parameters, supply voltages, and die temperatures, from which SPICE-compatible compact models are extracted and used further in circuit-level design and optimization.Related work:

  • S. Chen, Y. Wang, X. Lin, Q. Xie, and M. Pedram. “Performance prediction for multiple-threshold 7nm-FinFET-based circuits operating in multiple voltage regimes using a cross-layer simulation framework,” To appear in Proc. of IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, Oct. 2014.

Standard Cell Libraries and Circuit Synthesis for Deeply-Scaled FinFET Devices

A standard cell library containing timing and power information at different input and output conditions, i.e., input slew rates and output load capacitance, is required to enable logic synthesis, time and power analysis with the most advanced FinFET device technology. We generate 7nm FinFET device models by using Synopsys TCAD simulator and characterize standard cells through HSPICE simulations. Multiple supply voltages ranging from the near-threshold to the super-threshold regime are supported in our 7nm FinFET technology nodes, allowing both high performance and low power usage. In addition, devices with multiple threshold voltages are supported to enable multi-threshold technology. Synthesis results demonstrate that 7nm FinFET technology can achieve 15X circuit speed improvement and 350X energy consumption reduction, against the 45nm CMOS technology. 7nm FinFET standard cell libraries are available at here.

FinFET Sizing in Sub/Near-Threshold Regimes

FinFET has been proposed as an alternative for bulk CMOS in current and future technology nodes due to more effective channel control, reduced random dopant fluctuation, high ON/OFF current ratio, lower energy consumption, etc. Key characteristics of FinFET operating in the sub/near-threshold region are very different from those in the strong-inversion region. Therefore, FinFET sizing again becomes the focus of attention.

  • Logical Effort Method-Based FinFET Sizing and Independent Gate Control: We start from an analytical trans-regional FinFET model with high accuracy in both sub- and near-threshold regimes, and extend the well-known and widely-adopted logical effort delay calculation and optimization method to FinFET circuits operating in multiple voltage regimes. More specifically, a joint optimization of gate sizing and adaptive independent gate control is presented and solved in order to minimize the delay of FinFET circuits operating in multiple voltage regimes.
  • X. Lin, Y. Wang, and M. Pedram, “Joint sizing and adaptive independent gate control for FinFET circuits operating in multiple voltage regimes using the logical effort method,” in Proc. ICCAD, 2013.
  • Stack Sizing Analysis and Optimization of FinFET Logic Cells: We first improve the analytical trans-regional FinFET model to capture the drain current as a function of both the gate and drain voltages. We provide a detailed analysis on stack sizing of FinFET logic cells, and derive the optimal stack depth in FinFET circuits. Based on the stack sizing analysis, we propose a delay optimization framework for the FinFET circuits in the sub/near-threshold region.
  • X. Lin, Y. Wang, and M. Pedram, “Stack sizing analysis and optimization for FinFET logic cells and circuits operating in the sub/near-threshold regime,” in Proc. ISQED, 2014.

Life-Cycle Assessment of FinFET versus Bulk CMOS Technologies

The manufacturing of modern semiconductor devices involves a complex set of nanoscale fabrication process that are energy and resource intensive. It is important to understand and reduce the environmental impacts of manufacturing and usage of semiconductor circuits. We presented the first life-cycle energy and inventory analysis of FinFET integrated circuits and a comparative analysis with CMOS technology. A gate-to-gate inventory analysis is provided accounting for manufacturing, assembly, and use-phase. The functional unit used in this work is a (FinFET or CMOS) processor with the same functionality and performance level. Two types of applications are considered: high-performance servers and low-power mobile devices. The following conclusions are observed: (i) FinFET circuits achieve lower use-phase energy consumption compared with CMOS counterparts, and (ii) FinFET circuits can achieve less manufacturing and assembly energy because the effect of smaller size outweighs that of more complex manufacturing process.

Energy Efficient Memory Designs in Deeply-scaled Technologies

The aggressive down-scaling of transistors to the sub-10nm regime exacerbates short channel effects as well as device mismatches. Under such circumstances, conventional 6T SRAM cells made of bulk CMOS devices suffer from poor read and write stabilities. Accordingly, in order to improve the cell stability, at the device level, planar CMOS transistors are replaced with FinFET devices, and, at the circuit level, more robust SRAM structures such as the 8T SRAM cell are adopted. Our research thus focuses on the design of high yield (i.e., robust against process variations) and energy efficient FinFET-based cache memories. For this purpose, we use a cross-layer design and optimization framework spanning device, circuit, and architecture levels.

Architectural Analysis of Caches in Deeply-scaled Technologies — Future memory systems in deeply-scaled technologies (i.e., sub-10nm) necessitate FinFET support and more sophisticated SRAM cell structures. Accordingly, characteristics of SRAM cells need to be analyzed in order to find a desirable SRAM cell that simultaneously achieves high stability and low leakage power. Furthermore, evaluating such memory systems at the architecture-level requires modifications to the existing memory models and analysis tools. Hence, we developed P-CACTI which enhances CACTI by adding the following features:

  • Accurate technological parameters from advanced device simulators.
  • FinFET models for calculating transistor area, and gate/diffusion capacitances.
  • New technology nodes: 7nm FinFET and 14nm planar CMOS process technologies. Technology nodes refer to the gate (channel) length, and not the half metal pitch used in CACTI.
  • Updated interconnect parameters based on the ITRS 2012 data.
  • Dual-Vdd support: super- and near-threshold operating voltages.
  • Architectural support for the robust 8T SRAM cell.
  • FinFET-based SRAM cells with dual-gate control capability for enhancing the cell stability.
  • Configurable design parameters for FinFET-based SRAM cells.
  • XML-based interfaces for specifying the cache configuration, technological parameters of the adopted devices, and SRAM cell design.

Related work:

  • A. Shafaei, Y. Wang, X. Lin, and M. Pedram, “FinCACTI: Architectural Analysis and Modeling of Caches with Deeply-scaled FinFET Devices,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2014. (Best Paper Award)

Statistical Static Timing Analysis based on Efficient Current Source Modeling of FinFET Gates

Characteristics of FinFETs operating in the near/sub-threshold regime make it difficult to verify the timing of a circuit using conventional statistical static timing analysis (SSTA) techniques. Our work focuses on extending the CSM approach to handle VLSI circuits comprised of FinFET devices with independent gate control operating in the near/sub-threshold voltage regime and subject to process variations. In particular, we combine non-linear analytical models and low-dimensional CSM lookup tables to simultaneously achieve high modeling accuracy and time/space efficiency. The proposed model can be used to perform statistical static timing analysis (SSTA) based on the distribution of process variation parameters.Semi-Analytical CSM for FinFET Devices with Independent Gate Control

We develop a semi-analytical approach for FinFET CSM operating in the sub/near-threshold regime, accounting for the unit feature of independent gate control as well as process variations. The proposed technique determines all the component values in this equivalent circuit model given the applied voltages on the front-gate-controlled and back-gate-controlled fins, the output voltage, as well as process variation parameters for N-type and P-type FETs. Only 2D LUTs are needed in our semi-analytical method to reduce the storage space requirement.Related work:

  • T. Cui, Y. Wang, X. Lin, S. Nazarian, and M. Pedram. “Semi-analytical current source modeling for FinFET devices in multiple voltage regimes with independent gate control and process variations,” Proc. of Asia and South Pacific Design Automation Conference, Jan. 2014.

A Scalable CSM for Multiple-Input Cells

Another advantage of CSM over traditional STA models is that it can accurately capture the multiple-input switching (MIS) effect. The conventional multiple-input switching current source model (MCSM) is not scalable, since it requires high-dimensional lookup tables to account for all input, output, and internal node voltages (e.g., for a 3-input NAND gate, a 6-D lookup table is needed). We propose to model the current through each transistor in an m-input logic gate by building 2-D lookup tables with the key being Vgs and Vds of the transistor in question. Having looked up the current through all transistors in the design, we can then calculate the new output and internal node voltages.Related work:

  • T. Cui, S. Chen, Y. Wang, S. Nazarian, and M. Pedram. “An Efficient Semi-Analytical Current Source Model for FinFET Devices in Near/Sub-Threshold Regime Considering Multiple Input Switching and Stack Effect,” Proc. of Int’l Symposium on Quality Electronic Design, Mar. 2014.